1. Field of the Invention
The present invention relates to a semiconductor memory integrated circuit, and more particularly, to a redundancy fuse box of a semiconductor memory device and a method for arranging the same.
2. Background of the Prior Art
Highly integrated semiconductor devices include increasing numbers of redundancy cells that replace defective cells. Redundant cells are used to improve the yield in mass manufactured semiconductor device and consequently save on manufacturing costs.
A semiconductor memory cell array is generally constructed by a normal cell array and a redundancy cell array. In case defects are found in the normal cell, the defective normal cell is replaced with the redundancy cell by enabling a word line of the redundancy cell by an output of a redundancy fuse box. In order to replace the defective normal cell, the redundancy replacement cell is activated by a signal generated by cutting a fuse so as to reveal address information of the defective cell from a redundancy fuse box incorporated with an electric fuse.
FIG. 1 is a circuit diagram showing two conventional redundancy fuse box 20 arrangements known in the prior art. The first redundancy fuse box includes boxed portions 31 and 33 and buffer circuit 35. Portion 31 includes NMOS transistors 1, 3, . . . , 15 for gating addresses RA.sub.i (where i=0 to n), RA.sub.i B (where i=0 to n) and fuses connected to the NMOS transistors 1, 3, . . . , 15. Portion 33 includes PMOS transistors 21, 25 for precharging an output node (A), and buffer 35 for outputting a redundancy enable signal REDI by buffering a signal output from the output node (A).
The second redundancy fuse box includes boxed portions 71 and 73 and buffer circuit 75. Portion 71 includes NMOS transistors 41,43, . . . , 55 for gating addresses RA.sub.i (where i=0 to n), RA.sub.i B (where i=0 to n) and fuses connected to the NMOS transistors 41, 43, . . . , 55. Portion 73 includes PMOS transistors 61, 65 for precharging an output node (B). Buffer circuit 75 operates to output a redundancy enable signal RED2 by buffering a signal output from the output node (B).
The two fuse boxes shown in the drawing are separated from each other and operate individually.
FIG. 2A is a timing diagram showing the operation of a circuit in the situation where the fuse is not cut in the redundancy fuse box. The apparent signal lag times are not intended but are included solely to indicate the signal generating order.
As shown in FIG. 2A, when a PDPX signal becomes high during an active state of the fuse box, an A node latches to a high state by operation of PMOS transistor 21 and inverter 23. In such a state, if address signal RA.sub.i (where i=0 to n) becomes high, the A node transitions to a low state from a high state by operation of the NMOS transistor connected to the fuse operationally linked to address RA.sub.i. Consequently, the RED signal transitions to low from a high state.
Therefore, the now low RED signal activates a normal path and deactivates a redundancy path. During precharge, the PDPX signal becomes low after RA.sub.i becomes low, thus turning on PMOS transistor 25 and making the A node and RED node sequentially high.
FIG. 2B is a timing diagram showing the operation of the circuit in the situation where the fuse corresponding to a failed address is cut in the redundancy fuse box. Again, the apparent signal lag times arc not intended but are included solely to indicate the signal generating order.
Namely, when addresses RA.sub.0, RA.sub.1, . . . , RA.sub.i-1, and RA.sub.i are respectively in a high state and failure occurs, the fuses connected to RA.sub.0, RA.sub.1, . . . , RA.sub.i-1, and RA.sub.i are cut and the fuses of RA.sub.0 B, RA.sub.1 B, . . . , RA.sub.i-1 B, and RA.sub.i B are left intact. Thus, when PDPX becomes high, thereby latching the A node a high state by the operation of PMOS transistor 21 and inverter 23, the A node remains in a high state since the fuses connected to NMOS transistors 1, 5, 7 and 9 are cut. This occurs even though NMOS transistors 1, 5, 9 and 13, which correspond to high states at addresses RA.sub.0, RA.sub.i, . . . , RA.sub.i-1, and RA.sub.i, are turned on. Consequently, the RED signal remains in a high state while addresses RA.sub.0 B, RA.sub.1 B, . . . , RA.sub.i-1 B, and RA.sub.i B are all low.
Therefore, the high RED signal deactivates the normal path and activates the redundancy path. During precharge, the A node and RED remain in a high state even though the PDPX signal becomes low after the RA.sub.i address becomes low.
FIGS. 3 to 5 are block diagrams showing the conventional arrangement of the fuse box in a semiconductor memory. First, in a left side of a block diagram of FIG. 3, an address applied to a row decoder is gated with respect to fuse boxes 132 and 134. The fuse boxes 132 and 134 are arranged between the row decoders at a junction between a bit line (not shown) and a sense amplifier (not shown). An output of the fuse boxes, such as boxes 132 and 134, control any one, two, three, or four blocks, such as blocks 2, 4, 18 and 20, adjacent to the fuse box. Namely, the output of the fuse box 132 can be used even though any block has failed among the adjacent four blocks 2, 4, 18, and 20. Since the arrangement is symmetrical, the right portion in the block diagram is the same as that shown in the left portion.
The disadvantage of the conventional layout described above is that the fuse box must be laid out at the junction point between the bit line and the sense amplifier to be effective.
FIG. 4 shows a conventional symmetrical top to bottom fuse arrangement. In the upper block portion, a first fuse box 156, a second fuse box 158, a third fuse box 160, and a fourth fuse box 162 are each disposed between four blocks arranged in the horizontal direction of the chip. The output of the fuse boxes 156, 158, 160 and 162 passes through a peripheral circuit portion, connected to blocks 70 and 76, for applying redundancy information signals. The block redundancy is a method in which the redundancy information signals are collected in a block and a word line that has failed in another block is enabled in the block having a redundancy word line. Namely, as shown in FIG. 4, the line connected to the output port of the fuse boxes is determined according to the number of the fuse boxes. Therefore, if eight redundancy information signals are required for each of four arrays, at least sixteen lines should exist in each of the left and right directions. This exists because eight lines that pass the center of the chip are respectively formed in the upper portion and the lower portion. Thus, the size of the chip can be considerably affected.
A third conventional fuse/block arrangement is shown in FIG. 5. In the upper left portion of the block diagram of FIG. 5, fuse boxes 140 and 142 are arranged by extending the address line (not shown) applied to the row decoder to a peripheral circuit. The number of the address lines that can be extended to the peripheral circuit in a block is small due to the layout of repeated row decoders. As a result, only one fuse box 140 can be arranged in one block 36. Therefore, in FIG. 5, a second fuse box 142 is required to address one of the other blocks 34, 38, and 40. Furthermore, the address line extending from block 36 should be connected to the place where the second fuse box 142 is present or the address line should again be extended from the block 40 where the second fuse box 142 is present. Thus, the arrangement shown in FIG. 5 has a disadvantage in any case where the loading of the address line increases. Additionally, the RED line should be wired along the block as the number of the fuse boxes increase.
Each of these conventional fuse/block arrangements require additional wiring which is an inefficient use of chip real estate--a determiner of manufacturing cost. Accordingly, the need remains for an improved redundancy fuse box circuit over the prior art.